CN8380 Datasheet, PDF (17/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
1.0 Pin Descriptions
Table 1-1. Hardware Signal Definitions (1 of 5)
Pin Label
Signal Name I/O
Definition
RPOSO[1:4]
RDATO[1:4]
RNEGO[1:4]
BPV[1:4]
RCKO[1:4]
RTIP[1:4]
Receiver
RX Positive Rail
O Line rate data output on the rising or falling edge of RCKO. The clock edge
(Bipolar Mode)
is determined by the CLK_POL pin in Hardware Mode or the CLK_POL
register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high
RX Data (Unipolar
signal indicates receipt of a positive AMI pulse on RTIP/RRING inputs. In
Mode)
unipolar mode, RPOSO is redefined as RDATO and a high signal indicates
either a positive or negative AMI pulse on RTIP/RRING inputs.
RPOSO/RDATO is three-stated during device reset.
RX Negative Rail
(Bipolar Mode)
Bipolar Violation
(Unipolar Mode)
O Line rate data output on rising or falling edge of RCKO. The clock edge is
determined by the CLK_POL pin in Hardware Mode or the CLK_POL
register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high
signal indicates receipt of a negative AMI pulse on RTIP/RRING inputs. In
unipolar mode, RNEGO is redefined as BPV, and a high signal indicates the
reception of a BPV which is not part of a ZCS code (B8ZS or HDB3).
RNEGO/BPV is three-stated during device reset.
RX Clock Output
O Receive clock output. RCKO is the RPLL recovered line rate clock or jitter
attenuated clock output, based on the programmed jitter attenuator
selection. RCKO is three-stated during device reset.
Receive Tip
I Differential AMI data inputs for direct connection to receive transformer.
RRING[1:4]
Receive Ring
Transmitter
TPOSI[1:4]
TDATI[1:4]
TNEGI[1:4]
TCLK[1:4]
TACKI
EACKI
XOE[1:4]
TAIS[1:4]
Tx Positive Rail
(Bipolar Mode)
Tx Data (Unipolar
Mode)
Tx Negative Rail
Input
TX Clock Input
T1 AIS Clock
E1 AIS Clock
Transmit Output
Enable
Transmit AIS
Alarm
I Positive rail, line rate data source for transmitted XTIP/XRING output
pulses. Data is sampled on the falling edge of TCLK. In bipolar mode, a
high on TPOSI causes a positive output pulse on XTIP/XRING; and a high
on TNEGI causes a negative output pulse. In unipolar mode, TPOSI is
redefined as TDATI and accepts single-rail NRZ data. TNEGI is not used in
unipolar mode.
I Negative rail, line rate data input on TCLK falling edge. Refer to TPOSI
signal definition.
I/O Transmit line rate clock. TCLK is the transmit clock for TPOSI and TNEGI
data inputs and for transmitter timing. Normally, TCLK is an input and
samples TPOSI/TNEGI on the falling edge. In Host Mode, TCLK can be
configured as an output to supply a line rate transmit clock from the
CLAD. The timing reference for the TCLK output (and CLAD) can be
selected from six sources.
I Alternate T1 and E1 transmit clock used to transmit AIS (all 1s alarm
signal) when the primary transmit clock source, TCLK, fails. TACKI (T1) or
EACKI (E1) is either manually or automatically switched to replace TCLK
I [LIU_CTL; addr n3]. Systems without an AIS clock should connect TACKI
and EACKI to ground.
I^{P A low signal enables XTIP and XRING output drivers. Otherwise outputs}
are high impedance.
I^{P In Hardware Mode, a low signal causes AIS (unframed all 1s)}
transmission on XTIP/XRING outputs. In Host Mode, these pins can be
enabled or disabled [LIU_CTL; addr n3]. If disabled, they are not used and
may be left unconnected.
N8380DSA
Conexant
1-5
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