CN8380 Datasheet, PDF (20/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (4 of 5)
Pin Label
RLOS [1:4]
LLOOP [1:4]
RLOOP [1:4]
TDO
TDI
TMS
TCK
TRST
Signal Name
Receive Loss of
Signal
Local Loop
Remote Loop
Test Data Output
Test Data Input
Test Mode Select
Test Clock
Reset
I/O
Definition
O RLOS is asserted low when 100 (T1) or 32 (E1) consecutive 0s (no
pulses) are received at the line interface or when the received signal level
is approximately 18 dB below nominal for at least 1 ms.
I^{P These pins are always enabled in Hardware Mode and may be enabled or}
disabled in Host Mode [LIU_CTL; addr n3]. A low on LLOOP initiates Local
I^{P Analog Loopback and a low on RLOOP initiates Remote Line Loopback.}
Local Digital Loopback is initiated if both signals are asserted together.
Boundary Scan Signals (JTAG)
O Test data output per IEEE Std. 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic.
Updated on the falling edge of TCK.
I^{P Test data input per IEEE Std. 1149.1-1990. Used for loading all serial}
instructions and data into internal test logic. Sampled on the rising edge of
TCK. TDI may be left unconnected if not used.
I^{P Active-low test mode select input per IEEE Std 1149.1-1990. Internally}
pulled-up input signal used to control the test logic state machine.
Sampled on the rising edge of TCK. TMS may be left unconnected if not
used.
I^{P Test clock input per IEEE Std. 1149.1-1990. Used for all test interface and}
internal test-logic operations. If not used, TCK should be pulled low.
I^{P Active low reset. TRST is pulled up internally and may be left unconnected}
if not used.
Host Serial Control Signals
CS
SDI
SDO
SCLK
Chip Select
I^{P In Host Mode, CS is an active low input used to enable read/write access}
with the host serial control port. CS /JSEL(1) is a dual function pin.
Serial Data In
I^{P In Host Mode, SDI is the serial data input for the host serial control port.}
SDI/JSEL(2) is a dual function pin.
Serial Data Out
O In Host Mode, SDO is the serial data output for the host serial control port.
SDO/JATERR[1] is a dual function pin.
Serial Clock
I^{P In Host Mode, SCLK is the serial clock input for the host serial control}
port. SCLK/JDIR is a dual function pin.
Power Supply Pins and No-Connect Pins
VAA
Analog Supply
I +3.3 V + 5%. Power supply pair for the analog circuitry.
GND
VAAT[1:4]
GNDT[1:4]
VAAR
Ground
Tx Driver Supply
Ground
I +3.3 V + 5%. Power supply pairs for the transmitter driver circuitry. These
pin pairs should each be bypassed with a tantalum capacitor value of at
least 10 µF.
Rx Analog Supply I + 3.3 V + 5%. Power supply pair for the analog receiver circuitry.
GNDR
Ground
1-8
Conexant
N8380DSA
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