CN8380 Datasheet, PDF (47/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.7 Clock Rate Adapter
2.7 Clock Rate Adapter
The CLAD uses an input clock reference at a particular frequency (8 kHz to
16,384 kHz) to synthesize output clocks at a different frequency (8 kHz to 16,384
kHz). The CLAD outputs are frequency-locked to the selected timing reference.
The CLAD can operate with input reference frequencies at multiples and
submultiples of T1 or E1 line rates. The CLAD block diagram is illustrated in
Figure 2-10.
Figure 2-10. CLAD Block Diagram
CLADI
RCKO[1]
RCKO[2]
RCKO[3]
RCKO[4]
Clock
Monitor
Clock Rate Adapter (CLAD)
[G_T1/E1N]
[CPD_IE]
CLAD Control/
Status
[CPDERR]
[CPD_INT]
÷ [RSCALE] Factor
CLADR
Phase
Detector
Loop
Filter
[LFGAIN]
NCO
[FREE]
10 MHz
REFCKI
÷ [VSCALE] Factor
Device I/O Pin
CLADV
Labels in brackets [ ] refer
to register bits.
13
Refer to the following registers:
Global Configuration; addr 01
CLAD Configuration; addr 02
CLAD Frequency Select; addr 03
CLAD Phase Detector Scale Factor; addr 04
CLAD Status; addr 06
32.768 MHz
2.048 MHz
Divider Chain ^{1.544 MHz}
CLK32
CLK2048
CLK1544
CLADO
14
[CLK_OE]
N8380DSA
Conexant
2-25
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