CN8380 Datasheet, PDF (15/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
Figure 1-2. CN8380 Logic Diagram (Host Mode)
1.0 Pin Descriptions
Hardware/Host Mode
H^Ha^ar^rd^dw^waa^rr^ee^/HR^oe^sts^Met^ode I
Hardware Reset I
Local Loopback I
Local Loopback I
Remote Loopback I
Remote Loopback I
Host Mode
Host Mode
Hardware
HM
RES^HE^MT
RESET
LLOOP[1:4]
LLOOP[1:4]
RLOOP[1:4]
RLOOP[1:4]
InC^Htoe^{anrfrtardocwle a r e}
Control
Interface
IRQ
IRQ
RLOS[1:4]
RLOS[1:4]
Serial Data In I
Serial Data In I
Serial Clock In I
Serial Clock In I
Serial Chip Select I
Serial Chip Select I
Rece_Riv_ece_eT_ivi_ep_Tip I _I
Rece_Riv_ee_ceR_ivi_eng_Ring I _I
SDI
SDI
SCLK
SCLK
CS
CS
RTIP_R [_T1_{I P}:4_{[ 1}] _{: 4 ]}
RRI_RN_RG_{I N}[1_G:4_{[ 1}]_{: 4 ]}
Serial Port
I^Snt^ee^rrⁱf^aa^lce^{P o r t}
(S^{I n}E^tR^eI^rO^{f a})^{c e}
(SERIO)
SDO
SDO
R(_RRe(eRcCe_cCVievR_Vie_v)Rr_e)r
RCKO[1:4]
RCKO[1:4]
R_RP_PO_OS_SO_O [_[ 1_{1 :}:₄4_]]
R_RN_NE_EG_GO_O [_[ 1_{1 :}:₄4_]]
Trans_Tm_rai_nt_sC_ml_io_t c_Ck_locP_kIO_PIO
Transm_Tri_at_nP_smos_itit_Piv_oe_sitR_iva_e i_Rl _ail I _I
Transm_Tri_at_nN_smeg_ita_Nt_eiv_ge_atR_iva_e i_Rl _ail I _I
TCL_TK_C[_L1_K:4_{[ 1}] _{: 4 ]}
TPO_TS_P I_O[1_S:_I4_{[ 1}]_{: 4 ]}
TNEGI[1:4]
TNEGI[1:4]
T_Tra_{r a}n_nsm_{s m}itt_ie_t r_{t e r}
(X₍ M_{X M}TR_T )_{R )}
X_XT_TI_IP_P[_[1_{1 :}:₄4_]]
X_XR_RIN_{I N}G_G[_[1_{1 :}:₄4_]]
154₁4₅₄k₄H_Kz_HA_z l_Al _l1_l s_OnC_el_soc_Ck_lock I _I TAC_TK_AI_CKI
2048 kHz All 1s Clock
2048 KHz All Ones Clock
I
I
EAC_EK_AI_{C K I}
Transm_Tri_at _nO_smut_ip_{t O}ut_utE_pn_uta_Eb_nle_able I _I XOE_X[_O1_E:4_[1] _:4]
Tra_Tn_ras_nm_smit_itA_All_ll1_Os_nes I _I TAIS_T[1_A:_I4_S[]_1:4]
C_Clo_lc_ok_cR_k a_Rte_ate
A_Ada_dp_at_pe_tr_e(_rC₍L_CA_LD_A) _D)
CLADCLIAnDpuIntput I I CLACDLIADI
ReferReenfceerenCcleocCklock I I REFRCEKFICKI
CCLLKK 33 22
CCLLKK1155 44 44
CCLLKK2200 44 88
CCLLAADD OO
Test ^TC^el^so^tc^Ck^loI^cn^{k In} I ^I
Test M^Teo^sd^t e^MoS^de^ele^Sc^et^lect I ^I
Test^TD^ea^stta^DaIn^{ta In} I ^I
Test ^TR^ee^sts^Ret^esIn^{et In} I ^I
TCK^{T C K}
TMS^{T M S}
TDI ^TDI
TRS^TT^{R S T}
Bo_Bu_on_ud_na_dry_aS_{r y}ca_Sn_{c a n}
(JT₍A_JTG_A) _G)
T^TD^D O^O
O Interrupt Request
O Interrupt Request
O Receive Loss of Signal Status
O Receive Loss of Signal Status
O Serial Data Out
O Serial Data Out
O
O
Re_Rc_ee_ci_ev_ie_{v e}C_Clo_{l o}c_ck_k
O_O Re_Rc_ee_civ_eie_veP_Po_os_sit_iti_iv_ve_e R_Raa_ii_ll
O_O Re_Rc_ee_civ_eie_veN_Ne_eg_ga_at_ti_iv_ve_{e R}R_aa_ilil
O_O Tra_Tn_ras_nm_smit_itT_Tip_ip
O_O Tra_Tn_ras_nm_smit_iR_{t R}in_ing_g
OO 323.726.7868MMHHzzCClloockk OOuut t
OO T1TL1inLeineRRaateteCClloockk OOuut t
OO E1EL1inLeineRRaateteCClloocckk OOuut t
OO CLCALDADOOuutptpuutt
O^O Te^Ts^et ^sD^t a^Dt^aa^taO^Ou^ut^t
8380_004
I = Inp^Iu⁼t, ^IO^np=^utO^{, O}utp⁼u^Ot ^utput
PIO =^PP^Ir^Oog⁼ra^Pm^rom^ga^rab^mle^mI/^aO^{ble I/O}
N8380DSA
Conexant
1-3
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