CN8380 Datasheet, PDF (44/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

2.0 Circuit Description
2.6 Jitter Attenuator
CN8380
Quad T1/E1 Line Interface
2.6 Jitter Attenuator
The jitter attenuator (JAT) attenuates jitter in the receive or transmit path, but not
both simultaneously. The JAT path configuration and elastic store depth is
controlled by the JDIR and JSEL(2:0) pins in Hardware Mode or by the JEN,
JDIR, JCENTER, and JSIZE[2:0] bits in the Jitter Attenuator Configuration
register [JAT_CR; addr n0] in Host Mode. The JAT can also be completely
disabled.
The elastic store is configurable using the JSEL(2:0) pins or the JSIZE[2:0]
bits in the JAT_CR register. The elastic store sizes available are 8, 16, 32, 64, and
128 bits. The 32-bit elastic store depth is sufficient to meet jitter tolerance
requirements in all cases where the JAT cutoff frequency is 6 Hz or below, and
when the selected clock reference is frequency-locked. The larger elastic store
depths allow greater accumulated phase offsets. For example, the 128-bit depth
can tolerate up to ±64 bits of accumulated phase offset. Because the elastic store
is a fixed size, it can overflow and under-run. If either of these conditions occurs,
a Jitter Attenuator Elastic Store Limit Error (JATERR) is reported. In Hardware
Mode, JATERR[n] pins are provided, and in Host Mode, the JERR bit in the
Interrupt Status Register [ISR; addr n6] is set.
The elastic store is a circular buffer with independent read and write pointers.
These pointers can be initialized manually using JCENTER in the JAT_CR
register. JCENTER resets the write pointer and forces the elastic store read
pointer to one half of the programmed JSIZE. Centering is automatic as a result of
a JATERR condition, so manually centering is not required.
The dejittered receiver recovered clock is output on the RCKO[n] pin if the
JAT is configured in the receive path. The receiver input clock and data jitter
tolerance and jitter transfer meet TR 62411-1990. Figures 2-8 and 2-9 illustrate
jitter tolerance and JAT transfer characteristics.
2-22
Conexant
N8380DSA
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