CN8380 Datasheet, PDF (55/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
3.0 Registers
3.2 Global Control and Status Registers
3.2 Global Control and Status Registers
00—Device Identification (DID)
7
DID[7]
DID[7:4]
DID[3:0]
6
DID[6]
5
DID[5]
Device ID
Device Revision
4
DID[4]
3
DID[3]
2
DID[2]
1
DID[1]
R
0
DID[0]
01—Global Configuration (GCR)
7
RESET
6
G_T1/E1N
5
CLK_OE
4
CPD_IE
3
TCLK_I/O
2
CMUX[2]
1
CMUX[1]
R/W
0
CMUX[0]
RESET
G_T1/E1N
CLK_OE
CPD_IE
TCLK_I/O
Global Reset—When written to 1, initiates an internal global reset process which sets all
configuration registers to their default values for all four ports. Also, several output pins are
three-stated. After RESET is complete, the following is true:
• Digital receiver outputs (RPOSO[1:4], RNEGO[1:4], RCKO[1:4]) are three-stated.
• Transmitter line outputs (XTIP[1:4], XRING[1:4]) are three-stated.
• CLK1544, CLK2048, and CLADO clock outputs are three-stated.
• Transmitter clocks, TCLK[1:4] are configured as inputs.
• All interrupt sources are disabled.
• All configuration registers are set to default values.
Global Clock Mode—This bit selects one of two CLAD operating modes. The CLAD can
operate in a mode which insures the minimum output jitter on the CLK1544 output or the CLK
2048 output.
0 = CLK2048 output jitter minimized
1 = CLK1544 output jitter minimized
Clock Output Enable—Determines output state of CLK1544, CLK2048, and CLADO clock
outputs.
0 = Clock outputs are three-stated
1 = Clock outputs are enabled
CLAD Phase Detector Error Interrupt Enable—Enables CLAD loss of lock detector,
CPD_INT [CSTAT; addr 06], to generate an interrupt request.
0 = Interrupt disabled
1 = Interrupt enabled
Transmit Clock Input/Output—Determines whether TCLK[1:4] pins are inputs or outputs.
0 = TCLK[1:4] pins are inputs
1 = TCLK[1:4] pins are outputs
N8380DSA
Conexant
3-3
4/21/99
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