CN8380 Datasheet, PDF (27/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.2 Configuration and Control
Hardware Mode
Host Mode
CLK1544, CLK2048, and CLADO CLK1544, CLK2048, and CLADO
clock outputs are enabled.
clock outputs are three-stated.
Transmitter clocks, TCLK[1:4], are Transmitter clocks, TCLK[1:4], are
configured as inputs.
configured as inputs.
The IRQ pin is enabled (controlled The IRQ pin is three-stated.
by DPM).
All interrupt sources are disabled.
2.2.4.1 Power-on Reset
2.2.4.2 Hard Reset
2.2.4.3 Soft Reset
All configuration registers are set to
default values as listed in Section 3.1,
Address Map.
An internal power-on reset process is initiated during power-up. When VDD has
reached approximately 2.6 V, the internal reset process begins and continues for
300 ms maximum if REFCLK is applied. If REFCLK is not present, the CN8380
remains in the reset state.
Hard reset is initiated by bringing the RESET pin active (low). Once initiated, the
internal reset process completes in 5 µs maximum. If the RESET pin is held active
continuously, the clock and data outputs and the IRQ pin remain three-stated. The
following output pins are forced to high impedance while RESET is held active:
RPOSO[1:4]
RNEGO[1:4]
RCKO[1:4]
XTIP[1:4]
XRING[1:4:]
CLK1544
CLK2048
CLADO
TCLK[1:4]
IRQ
RLOS[1:4]
JATERR[1:4]
SDO
TDO
In Host Mode, soft reset is initiated by writing a one to the RESET bit in the
Global Configuration register [addr 01]. The RESET bit is self-clearing. Once
initiated, the internal reset process completes in 5 µs maximum and the device
enters normal operation.
N8380DSA
Conexant
2-5
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