CN8380 Datasheet, PDF (16/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Figure 1-3. CN8380 Logic Diagram (Hardware Mode)
VDD
Hardware/Host Mode
Hardware Reset I
Jitter Attenuator Path I
Jitter Attenuator Size I
Unipolar/Bipolar I
Transmitter Termination I
Transmit Pulse Template I
Clock Polarity I
Raw Mode Select I
Local Loopback I
Remote Loopback I
Zero Code Suppression I
Receive Tip I
Receive Ring I
Hardware Mode
Hardware
Control
HM
Interface
RESET
JDIR
JSEL(2:0)
UNIPOLAR
IRQ
HTERM
JATERR[1:4]
PTS(2:0)
RLOS[1:4]
CLK_POL
RAWMD[1:4]
LLOOP[1:4]
RLOOP[1:4]
ZCS
Receiver
(RCVR)
RTIP[1:4]
RRING[1:4]
RCKO[1:4]
RPOSO[1:4]
RNEGO[1:4]
Transmit Clock I
Transmit Positive Rail I
Transmit Negative Rail I
1544 kHz All 1s Clock I
2048 kHz All 1s Clock I
Transmit Output Enable _I
Transmit All 1s I
Transmitter
TCLK[1:4] ^(XMTR)
TPOSI[1:4]
TNEGI[1:4]
XTIP[1:4]
XRING[1:4]
TACKI
EACKI
XOE[1:4]
TAIS[1:4]
CLAD Input I
Reference Clock I
Clock Rate
Adapter (CLAD)
CLADI
REFCKI
CLK32
CLK1544
CLK2048
CLADO
Test Clock In I
Test Mode Select I
Test Data In I
Test Reset In I
TCK
TMS
TDI
TRST
Boundary Scan
(JTAG)
TDO
O Interrupt Request
O Jitter Attenuator Error Status
O Receive Loss of Signal Status
O Receive Clock
O Receive Positive Rail
O Receive Negative Rail
O Transmit Tip
O Transmit Ring
O 32.768 MHz Clock Out
O T1 Line Rate Clock Out
O E1 Line Rate Clock Out
O 8 KHz Clock Out
O Test Data Out
I = Input, O = Output
PIO = Programmable I/O
1-4
Conexant
N8380DSA
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