CS4237B Datasheet, PDF (92/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
Line Level Outputs
The analog output section provides a stereo line-
level output. The other output types (headphone
and speaker) can be implemented with external
circuitry. LOUT and ROUT outputs should be
capacitively coupled to external circuitry. Both
LOUT and ROUT need 1000 pF NPO capacitors
between the pin and AGND.
Mono Output with Mute Control
The mono output, MOUT, is a sum of the left
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
channel can be used to drive the PC-internal
mono speaker using an appropriate drive circuit.
This approach allows the traditional PC-sounds
to be integrated with the rest of the audio sys-
tem. Figure 30 illustrates a typical speaker driver
circuit. The mute control is independent of the
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The
power-up default has MIN connected to MOUT
providing a pass-through for the beeps heard at
power-up.
+5V
Ferrite Bead
470 pF
MOUT
0.1 µF
10 kΩ
0.22 µF _{1 µF +}
46
3
21 ⁷
5 ^{16 kΩ}
8
RESDRV
MC34119
or LM4861
Figure 30. Mono Output
the ADCs. By placing these filters at the input to
the ADCs, low-pass filters at each analog input
pin are avoided.
The REFFLT pin is used to lower the noise of
the internal voltage reference. A 1µF (must not
be greater than 1µF) and 0.1µF capacitor to ana-
log ground should be connected with a short
wide trace to this pin. No other connection
should be made, as any coupling onto this pin
will degrade the analog performance of the
codec. Likewise, digital signals should be kept
away from REFFLT for similar reasons.
The VREF pin is typically 2.2 V and provides a
common mode signal for single-supply external
circuits. VREF only supports light DC loads and
should be buffered if AC loading is needed. For
typical use, a 0.1 µF in parallel with a 10 µF ca-
pacitor should be connected to VREF.
GROUNDING AND LAYOUT
Figure 31 is a suggested layout for motherboard
designs and Figure 32 is a suggested layout for
add-inn cards. For optimum noise performance,
the device should be located across a split ana-
log/digital ground plane. The digital ground
plane should extend across the ISA bus pins as
well as the internal digital interface pins.
DGND1 is ground for the data bus and should
be electrically connected to the digital ground
plane which will minimize the effects of the bus
Miscellaneous Analog Signals
The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capaci-
tors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to
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