CS4237B Datasheet, PDF (35/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
Capture I/O Data Register
(WSSbase+3, R3, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD7-CD0
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data trans-
fers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once the Status register (R2) is read and a new
sample is received from the FIFO, the state ma-
chine and Status register (R2) will point to the
first byte of the new sample.
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
Playback I/O Data Register
WSSbase+3, R3, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD7-PD0
Playback Data Port. This is the control
register where playback data is
written during programmed IO data
transfers.
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read, and the current sam-
ple is sent to the DACs via the FIFOs.
INDIRECT MAPPED REGISTERS
These registers are accessed by placing the ap-
propriate index in the Index Address register
(R0) and then accessing the Indexed Data regis-
ter (R1). A detailed description of each indirect
register is given below. All reserved bits should
be written zero and may be 0 or 1 when read.
Note that indirect registers 16-31 are not avail-
able when in MODE 1 (CMS1,0 in MODE and
ID register I12 are both zero).
Left ADC Input Control (I0)
Default = 000x0000
D7 D6 D5 D4 D3
LSS1 LSS0 LMGE res LAG3
D2
LAG2
D1
LAG1
D0
LAG0
LAG3-LAG0
res
Left ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 7.
Reserved. Must write 0. Could read
as 0 or 1.
LMGE
This bit has no function in MODE 3.
In MODEs 1 & 2 it controls the
20 dB gain boost for the left MIC in-
put to the ADC.
LSS1-LSS0
Left output loopback. In MODE 3,
setting these bits to 11 enables the
left output loopback into the input
mixer. Bit combinations of 01, 10,
and 00 disable the loopback.
In MODEs 1 & 2, the input mixer is
used as a multiplexer where these
bits select the left ADC input source.
00 - LLINE
01 - LAUX1
10 - LMIC
11 - Left Output Mixer Loopback
DS213PP4
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