CS4237B Datasheet, PDF (106/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
Volume Control
The volume control pins are enabled by setting VCEN in the Hardware Configuration data,
Misc. Hardware Config. byte. The VCF1,0 bits in the Hardware Configuration data, Global
Configuration byte, set the format for the volume control pins. Each pin must have an external
pullup resistor (10kΩ) and either a momentary or toggle style switch based on format. Typically
a 100Ω series resistor and a capacitor to ground, capacitor on the switch side of the series
resistor, would be included on each pin for ESD protection and to help with EMI emissions.
UP - Volume Up
The SCS/UP pin is multiplexed with the external Synthesizer chip select. This pin is switched
to the UP function when VCEN is set. When UP is low, the master volume output for left and
right channels are incremented.
DOWN - Volume Down
The XCTL1/SINT/ACDCS/DOWN is a multiplexed pin that can be used as XCTL1, the
external FM synthesizer interrupt, the alternate CDROM chip select, or the Volume Down pin.
This pin is switched to the DOWN function when VCEN is set. When DOWN is low, the
master volume output for left and right channels are decremented.
MUTE - Volume Mute
The MUTE pin function can be toggle, momentary, or non-existent based on the VCF1,0 bits.
The MUTE function is enabled when VCEN is set.
Miscellaneous
XTALI - Crystal Input
This pin will accept either a crystal, with the other pin attached to XTALO, or an external
CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The
crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance
operation.
XTALO - Crystal Output
This pin is used for a crystal placed between this pin and XTALI. If an external clock is used
on XTALI, this pin must be left floating with no traces or components connected to it.
RESDRV - Reset Drive, Input
Places the part in lowest power consumption mode. All sections of the part are shut down and
consuming minimal power. The part is reset and in power down mode when this pin is logic
high. The falling edge also latches the state of XIOR and XIOW to determine the functionality
of dual mode pins. This signal is typically connected to the ISA bus signal RESDRV. RESDRV
must be asserted whenever the part is powered up to initialize the internal registers to a known
state. This pin, when high, also drives the BRESET pin low.
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