CS4237B Datasheet, PDF (75/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
CDROM Interface
An IDE CDROM controller interface is provided
that supports Enhanced as well as Legacy IDE
CDROM drives. This interface includes two pro-
grammable chip selects and on-chip hardware to
map DMA and interrupt signals to the ISA bus.
There are five pins that make up the CDROM
interface which consist of:
CDCS - chip select, COMbase address
CDINT - interrupt, COMint
CDRQ - DMA request, COMdma
CDACK - DMA acknowledge, COMdma
ACDCS - alternate chip select, ACDbase
The four basic CDROM interface pins are multi-
function pins that default to the upper address
bits SA12 - SA15. To use the pins as a CDROM
interface, a pulldown resistor must be placed on
XIOR (XIOR must be buffered if driving TTL
logic). Once the CDROM interface is selected,
the CDROM DMA pins are further multiplexed
with the Modem pins. Therefore, a fifth logical
device, typically a modem, can be used if the
CDROM doesn’t support DMA. See the Modem
Interface section for more details.
The fifth CDROM pin ACDCS is multiplexed
with XCTL1/SINT/DOWN. This chip select sup-
ports the alternate CDROM chip select used for
status in legacy IDE drives. The volume control
pin DOWN has the highest precedence; there-
fore, the VCEN bit must be zero to use this pin
for the CDROM interface. Given that VCEN is
zero, if the base address for ACDCS, which is
ACDbase, is programmed to a non-zero value,
this pin converts to ACDCS. ACDbase, base ad-
dress 1 in LD4, is programmed via PnP or via
the SLAM method. Once this pin is set to
ACDCS, the only way to revert to XCTL1 or
SINT is to reset the part. The range of addresses
that ACDCS will respond to is programmable
via the Hardware Configuration data, byte 5,
from one to eight bytes. The default is 1 byte. In
legacy IDE CDROM drives, the alternate
CDROM address plus 1, ACDbase+1, is typi-
cally shared with the floppy controller, which
only drives data bit 7. Therefore, a bit in the
Hardware Configuration data keeps the SD7 pin
from driving data bit 7 when that address is de-
coded. This bit is labeled ACDB7D and is
located in the Hardware Configuration data, byte
7. When using ACDCS, the SINT function
should be selected and a pullup placed on this
line, which will allow this pin to powerup inac-
tive. If XCTL1 is selected, it will powerup low;
therefore, ACDCS will be low until ACDbase is
programmed to a non-zero value.
The default address space for the peripheral port
is 4 I/O locations where XCTL0/XA2 defaults to
the control pin XCTL0. To use XCTL0/XA2 as
the XA2 address pin, thereby increasing the ad-
dress range of the peripheral port to 8 locations,
the hardware resource data must be changed. See
the Hardware Configuration Data section. Even
though the default address space is only 4 loca-
tions, the alignment for CDbase must be a
division of 8.
To make the CDROM interface more flexible,
two global bits, located in the Hardware Con-
figuration data section - byte 7, allow control
over the polarity of the CDROM interrupt pin
CDINT, and whether the SD<7-0> pins drive the
ISA bus or not. The first bit is IHC which de-
faults to 1 indicating that CDINT is an active
high interrupt. IHC is also controllable through
CTRLbase+1. The second bit is SDD - SD<7:0>
bus Disable. When this bit is set, the part will
not drive the ISA Data bus SD<7:0> pins, on
reads from either CDbase or ACDbase addresses.
This bit allows external data buffers to be used
for a CDROM that bypasses the XD<7:0> bus
and connects directly to the ISA bus. Note that
SDD affects any peripheral port device which in-
cludes the external FM and modem interfaces.
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