CS4237B Datasheet, PDF (23/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
HW Config. Byte 8: Global Configuration Bits,
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
IFM VCF1 VCF0 SLAD WTEN SPS res res
res
Must be set to zero to allow compat-
ibility with future upgrades.
SPS
DSP Serial Port Switch. When
set, switches the DSP serial port
pins from the second joystick to the
XD4-XD1 pins. Then, when SPE in
I16 is set, the XD4-XD1 pins convert
to the DSP serial port pins. Once
this bit is enabled, the SD bus will
not be driven when accesses occur
to peripheral port devices. This func-
tion is also available in C8.
WTEN
WaveTable Serial Port Enable. When
set, forces XD7-XD5 pins to convert
to the CS9236 Single-Chip Wave-
table Music Synthesizer serial port
pins. Once this bit is enabled, the
SD bus will not be driven when ac-
cesses occur to peripheral port
devices. This function is also avail-
able in C8.
SLAD
Soundblaster Alternate Line Disable.
When clear, Sound Blaster (SB)
Synthesizer Volume changes affect
the LINE Alternate (X0/X1) volume.
When set, SB Synthesizer Volume
changes do not affect X0/X1 regis-
ters.
VCF1,0
Hardware Volume Control Format.
These bits control the format of the
hardware volume control pins UP,
DOWN, and MUTE. The volume con-
trol is enabled by setting VCEN in
the previous Hardware Configuration
byte.
00 - MUTE is a toggle switch. When
MUTE is low, the volume is muted.
01 - MUTE is a momentary switch.
MUTE toggles between mute and
un-mute. Pressing the up or down
switch always un-mutes.
10 - MUTE is not used. Two button
volume control. Pressing the up
and down buttons simultaneously
causes the volume to mute.
Pressing up or down un-mutes.
11 - UP pin is not used. The
MUTE pin functions as the Up
function. With this exception, this
mode functions similarly to the
pervious two-button mode. This
mode provides backwards
compatibility with the CS4236.
IFM
Internal FM. When set, the internal
FM synthesizer is enabled. When
clear, FM must be provided on the
external LINE analog inputs.
HW Config. Byte 9: Code Base Byte,
Default = 00001011
D7 D6 D5 D4 D3 D2 D1 D0
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
CB7-CB0
Code Base Byte. Determines the code
base located in the E²PROM. If not
correct, the Firmware code after the
PnP resource data is not loaded.
0x0B - CS4237B
0x43 - CS4236
The next 7 bytes are reserved for future expan-
sion and must be set to their default values as
listed in Table 2
The next byte of hardware configuration data is
byte 17 in Table 2. This byte determines the
function of the XCTL0/XA2 pin. The default of
0, forces the pin to the control function XCTL0,
and the external peripheral port supports only 4
I/O locations through XA0-XA1. If this byte is
set to 08h, the pin switches to the XA2 function
and the peripheral port supports 8 I/O locations
through XA2-XA0.
The next byte, listed as byte 18, is reserved for
future expansion and must be set to 0x48.
DS213PP4
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