CS4237B Datasheet, PDF (33/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
Index Address Register
(WSSbase+0, R0)
D7 D6 D5 D4 D3 D2 D1 D0
INIT MCE TRD IA4 IA3 IA2 IA1 IA0
IA3-IA0
Index Address: These bits define the
address of the indirect register ac-
cessed by the Indexed Data register
(R1). These bits are read/write.
IA4
Allows access to indirect registers 16
- 31. In MODE 1, this bit is re-
served and must be written as zero.
TRD
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
capture DRQs occur uninhibited)
1 - Transfers Disabled (playback and
capture DRQ only occur if INT bit
is 0)
MCE
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
INIT
WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indi-
cates unknown).
During initialization and software power down
(PM1,0 = 01), this register CANNOT be written
and always reads 10000000 (80h)
Indexed Data Register
(WSSbase+1, R1)
D7 D6 D5 D4 D3 D2 D1 D0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
ID7-ID0
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
Status Register
(WSSbase+2, R2, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CU/L CL/R CRDY SER PU/L PL/R PRDY INT
INT
Interrupt Status: This indicates the
status of the internal interrupt logic
of the WSS Codec. This bit is
cleared by any write of any value to
this register. The IEN bit of the Pin
Control register (I10) determines
whether the state of this bit is re-
flected on the IRQ pin assigned to
the WSS Codec.
Read States
0 - Interrupt inactive
1 - Interrupt active
PRDY
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when di-
rect programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
DS213PP4
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