CS4237B Datasheet, PDF (7/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
TIMING PARAMETERS (T_A = 25 °C; VA, VD1, VDF1-VDF4 = +5V; outputs loaded with 30pF
Input Levels: Logic 0 = 0V, Logic 1 = VD1)
Parameter
E²PROM Timing (Note 1)
Symbol
Min
Max
Units
SCL Low to SDA Data Out Valid
tAA
0
3.5
µs
Start Condition Hold Time
t_HD:STA
4.0
-
µs
Clock Low Period
tLSCL
4.7
-
µs
Clock High Period
t_HSCL
4.0
-
µs
Start Condition Setup Time
(for a Repeated Start Condition)
tSU:STA
4.7
-
µs
Data In Hold Time
t_HD:DAT
0
-
µs
Data In Setup Time
tSU:DAT
250
-
ns
SDA and SCL Rise Time
(Note 7) tR
-
1
µs
SDA and SCL Fall Time
t_F
-
300
ns
Stop Condition Setup Time
tSU:STO
4.7
-
µs
Data Out Hold Time
tDH
0
-
ns
Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the
external pullup resistor required.
XA0/SCL
t _SU:STA
XD0/SDA (IN)
XD0/SDA (OUT)
tF
tHSCL
tLSCL
t _HD:STA t _HD:DAT
t _SU:DAT
t _AA
tDH
E²PROM 2-Wire Interface Timing
tR
t _SU:STO
DS213PP4
7