CS4237B Datasheet, PDF (74/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
volume is applied to the PCM FM data, it is
summed into the digital mixer which is then
summed into the analog output mixer.
For backwards compatibility with analog-mixed
external FM devices, I18 and I19 in the WSS
logical device can be remapped to control the
volume of internal FM. Remapping is controlled
through the FMRM bit in X4 register. When
IFM = 1, and FMRM = 1, writes to I18 and I19
are remapped to X6 and X7 respectively. When
remapping is enabled, the LINE analog input
volume is controlled through X0/1. When
FMRM = 0, internal FM volume is only control-
led through X6/7.
The synthesizer interface is compatible with the
Adlib and Sound Blaster standards. The typical
Adlib I/O address is SYNbase = 388h.
Standard Adlib Synthesizer I/O Map
Address
Name
Type
SYNbase+0
FM Status
SYNbase+0 FM Address 0
Read Only
Write Only
SYNbase+1
FM Data 0
Write Only
SYNbase+2 FM Address 1
SYNbase+3
FM Data 1
Write Only
Read Only
EXTERNAL PERIPHERAL PORT
An external peripheral port is provided for inter-
facing devices external to the part. These may
include the CS9233 Wavetable synthesizer,
CDROM interface, modem interface, and Plug
and Play E²PROM.
The External Peripheral Port consists of the fol-
lowing signals: 8-bit data bus, 2 or 3 address
lines, read strobe, write strobe, and reset signal.
External Synthesizer Interface
This part contains an internal FM synthesis en-
gine. For backwards compatibility the default is
to use an external FM-type synthesizer chip such
as the Yamaha OPL3LS, or the Crystal Semicon-
ductor CS9233 wave-table synthesizer chip. This
interface consists of:
SCS - chip select
SINT - Synthesizer Interrupt
The other signals such as address bits, data
strobes, data, and reset are provided by the Ex-
ternal Peripheral Port. The interface allows the
host computer to access up to eight I/O mapped
locations. When using an external FM synthe-
sizer, SCS will respond to the SYNbase decode
addresses as well as the SBPro mapped FM syn-
thesizer addresses. The PnP synthesizer
alignment must be a multiple of 8.
The polarity of SINT is programmable via Hard-
ware Configuration data, IHS in byte 7, or
through CTRLbase+1. The default is active low
(IHS = 0).
Since the typical FM interface only requires four
I/O address and does not use an interrupt, the
XA2 address and the SINT pins are multifunc-
tion pins that default to XCTL0 and XCTL1. To
use XCTL0/XA2 as an address pin, the hardware
resource data must be changed. See the Hard-
ware Configuration Data section for more
information. To use XCTL1/SINT/ACDCS/
DOWN as an interrupt for the synthesizer,
VCEN (in the Hardware Configuration data)
must be zero, a pulldown resistor must be placed
on the XIOW pin. Since XCTL1 and SINT are
rarely used the pin has a third multiplexed func-
tion, ACDCS, which is described in the
CDROM section below. The fourth multiplexed
function is the hardware volume control pin
DOWN which is controlled through the VCEN
bit. See the Volume Control Interface section for
more details. Note that ACDCS takes precedence
over XCTL1/SINT. Also DOWN, when VCEN
is set, takes precedence over all other functions.
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