CS4237B Datasheet, PDF (63/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

CS4237B
Block Power Down
CTRLbase+2, Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
PDWN SRC VREF MIX ADC DAC PROC FM
FM
Internal FM synthesizer powered down
when set.
PROC
Processor set to idle mode. When set,
places the internal processor in an
idle state. This effects the PnP inter-
face, MPU401, and SBPro devices.
Any command to any one of these
interfaces will cause the processor
to go active.
DAC
DAC power down. When set, powers
down the D/A converters, serial
ports, and internal FM synthesizer.
The DACs should be muted prior to
setting this bit to prevent audible
pops.
ADC
ADC power down. When set, powers
down the A/D Converters.
MIX
Mixer power down. All analog input
and output channels are powered
down, except MIN and MOUT (as-
suming VREF is not powered down).
If MIX is 1 and VREF is 0, the MBY
bit in the WSS I26 register is forced
on. The outputs should be muted
prior to setting this bit to prevent
audible pops.
VREF
VREF power down. When set, powers
down the entire mixer. Since
powering down VREF, powers down
the entire analog section, some audi-
ble pops can occur.
SRC
Internal Sample-Rate Converters are
powered down. Only 44.1 kHz sam-
ple frequency is allowed when this
bit is set.
PDWN
Global Power Down. When set, the
entire chip is powered down, except
reads and writes to this register.
When this bit is cleared, a full cali-
bration is initiated. All registers retain
their values; therefore, normal opera-
tion can resume after calibration is
completed. When clearing this bit,
the internal processor stays in power-
down until accesses occur to
processor interface (Sound Blaster,
MPU, or PnP accesses). If hardware
volume control is enabled, this bit
should be written to 0 twice causing
the processor to go active (which
reenables the hardware volume).
NOTE: Software should mute the DACs and Mixers
and FM volume when asserting any power down
modes to prevent clicks and pops.
Control Indirect Address Register
CTRLbase+3
D7 D6 D5 D4 D3 D2 D1 D0
res res res res CA3 CA2 CA1 CA0
CA3-CA0
res
Address bits to access the Control
Indirect registers C0-C8 through
CTRLbase+4
Reserved. Could read as 0 or 1.
Must write as 0.
Control Indirect Data Register
CTRLbase+4
D7 D6 D5 D4 D3 D2 D1 D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD7-CD0
Control Indirect Data register. This
register provides access to the indi-
rect registers C0-C8, where
CTRLbase+3 selects the actual reg-
ister. See the Control Indirect
Register section for more details.
DS213PP4
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