CS4237B Datasheet, PDF (34/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

PL/R
PU/L
SER
CRDY
CS4237B
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel in
all data formats except ADPCM. In
ADPCM it indicates whether the first
two or last two bytes of a 4-byte set
(8 ADPCM samples) are needed.
0 - Right or 3/4 ADPCM byte needed
1 - Left, Mono, or 1/2 ADPCM byte
needed
Playback Upper/Lower Byte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel. In ADPCM it in-
dicates, along with PL/R, which one
of the four ADPCM bytes is needed.
0 - Lower or 1/3 ADPCM byte needed
1 - Upper, any 8-bit format, or 2/4
ADPCM byte needed.
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indi-
cates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
be determined. However, the Alter-
nate Feature Status register (I24)
can indicate the exact source of the
error.
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the host. This
bit would be used for direct pro-
grammed I/O data transfers.
0 - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
CL/R
CU/L
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel in all audio data for-
mats except ADPCM. In ADPCM it
indicates whether the first two or last
two bytes of a 4-byte set (8 ADPCM
samples) are waiting.
0 - Right or 3/4 ADPCM byte available
1 - Left, Mono, or 1/2 ADPCM byte
available
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel. In ADPCM it indi-
cates, along with CL/R, which one of
four ADPCM bytes is available.
0 - Lower or 1/3 ADPCM byte
available
1 - Upper, any 8-bit format, or 2/4
ADPCM byte available
Note on PRDY/CRDY: These two bits are de-
signed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
I/O DATA REGISTERS
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During initialization and software power down
of the WSS Codec, this register CANNOT be
written and is always read 10000000 (80h)
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