CS4237B Datasheet, PDF(29/114 Page) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

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CS4237B Datasheet, PDF (29/114 Pages) Cirrus Logic – CrystalClear Advanced Audio System with 3D Sound

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CS4237B

Sound System Codec Register Interface

The Windows Sound System codec is mapped

via four locations. The I/O base address,

WSSbase, is determined by the Plug and Play

configuration. The WSSbase supports four direct

registers, shown in Table 3. The first two direct

registers are used to access 32 indirect registers

shown in Table 4. The Index Address register

(WSSbase+0) points to the indirect register that

is accessed through the Indexed Data register

(WSSbase+1).

This section describes all the direct and indirect

registers for the WSS Codec. Table 5 details a

summary of each bit in each register with Ta-

bles 6 through 15 illustrating the majority of

decoding needed when programming the WSS

logical device, and are included for reference.

When enabled, the WSS Codec default state is

defined as MODE 1. MODE 1 is backwards

compatible with the CS4248 and only allows ac-

cess to the first 16 indirect registers. Putting the

part in MODE 2 or MODE 3, using CMS1,0 bits

in the MODE and ID register (I12), allows ac-

cess to indirect registers 16 through 31. Putting

the part in MODE 3 also allows access to the

extended registers through I23 and other ex-

tended features in the indirect registers.

DIRECT MAPPED REGISTERS

The first two WSS Codec registers provide indi-

rect accessing to more codec registers via an

index register. The other two registers provide

status information and allow audio data to be

transferred to and from the WSS Codec without

using DMA cycles or indexing.

Note that register defaults are listed in binary

form with reserved bits marked with âxâ to indi-

cate unknown. To maintain compatibility with

future parts, these reserved bits must be written

as 0, and must be masked off when the register

is read. The current value read for reserved bits

is not guaranteed on future revisions.

Direct Registers: (R0-R3)

Address

WSSbase+0

WSSbase+1

WSSbase+2

WSSbase+3

Reg.

Index Address register

Indexed Data register

Status register

PIO Data register

Table 3. WSS Codec Direct Register

Index

I10

I11

I12

I13

I14

I15

I16

I17

I18

I19

I20

I21

I22

I23

I24

I25

I26

I27

I28

I29

I30

I31

Left ADC Input Control

Right ADC Input Control

Left Aux #1 Volume

Right Aux #1Volume

Left Aux #2 Volume

Right Aux #2 Volume

Left DAC (PC Wave) Volume

Right DAC (PC Wave) Volume

Fs & Playback Data Format

Interface Configuration

Pin Control

Error Status and Initialization

MODE and ID

Monitor Loopback Volume

Playback Upper Base Count

Playback Lower Base Count

Alternate Feature Enable I

Alternate Feature Enable II

Left Line (Synthesizer) Volume

Right Line (Synthesizer) Volume

Timer Low Byte

Timer High Byte

Alternate Sample Frequency

Extended Register Access (X regs)

Alternate Feature Status

Compatibility ID

Mono Input & Output Control

Reserved

Capture Data Format

Reserved

Capture Upper Base Count

Capture Lower Base Count

Table 4. WSS Codec Indirect Registers

DS213PP4

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