T32UC3L0128_14 Datasheet, PDF (725/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

30.7.2 Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x04
Reset Value:
0x00000000
AT32UC3L0128/256
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
TRMIS
-
-
OVERRUN DREADYINT READYINT
7
6
5
4
3
2
1
-
-
-
-
-
CENABLED
-
• TRMIS: Transmit Mismatch
0: No transfers mismatches.
1: The transceiver was active when receiving.
This bit is set when the transceiver is active when receiving.
This bit is cleared when corresponding bit in SCR is written to one.
• OVERRUN: Data Overrun
0: No data overwritten in RHR.
1: Data in RHR has been overwritten before it has been read.
This bit is set when data in RHR is overwritten before it has been read.
This bit is cleared when corresponding bit in SCR is written to one.
• DREADYINT: Data Ready Interrupt
0: No new data in the RHR.
1: New data received and placed in the RHR.
This bit is set when new data is received and placed in the RHR.
This bit is cleared when corresponding bit in SCR is written to one.
• READYINT: Ready Interrupt
0: The interface has not generated an ready interrupt.
1: The interface has had a transition from busy to not busy.
This bit is set when the interface has transition from busy to not busy.
This bit is cleared when corresponding bit in SCR is written to one.
0
BUSY
• CENABLED: Clock Enabled
0: The aWire clock is not enabled.
1: The aWire clock is enabled.
32145C–06/2013
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