T32UC3L0128_14 Datasheet, PDF (554/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

AT32UC3L0128/256
23.7.13 Interlinked Single Value Channel Set
Name:
ISCHSETm
Access Type:
Write-only
Offset:
0x30+m*0x10
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
SET
23
22
21
20
19
18
17
16
SET
15
14
13
12
11
10
9
8
SET
7
6
5
4
3
2
1
0
SET
• SET: Single Value Channel Set
If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY.
If more than one ISCHSET register is present, ISCHSET0 controls channels 31 to 0 and ISCHSET1 controls channels 63 to 32.
Note:
The duty registers will be updated with the value stored in the ISDUTY register when any ISCHSETm register is written. Syn-
chronization takes place immediately when an ISCHSET register is written. The duty cycle registers will, however, not be
updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches.
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