T32UC3L0128_14 Datasheet, PDF (479/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

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Figure 21-10. User Sends Data While the Bus is Busy
TWCK
TWD
TWI DATA transfer
STOP sent by the master
START sent by the TWI
DATA sent by a master
Bus is busy
Transfer is kept
Bus is free
DATA sent by the TWI
A transfer is programmed
(DADR + W + START + Write THR)
Figure 21-11. Arbitration Cases
TWCK
TWD
Bus is considered as free
Transfer is initiated
TWCK
Data from a Master
Data from TWI
TWD
S 1 0 0 11
P
S 101
Arbitration is lost
TWI stops sending data
S 1 0 0 _{1 1} Data from the master P
Arbitration is lost
S 101
The master stops sending data
S 1 0 01 ₁
S 1 0 0 1 1 Data from the TWI
ARBLST
Bus is busy
Bus is free
TWI DATA transfer
Transfer is kept
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
21.8.7
Combined Transfers
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause
a REPEATED START on the bus. The ability to generate such connected transfers allows arbi-
trary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is
done in master receiver mode, the CMDR.ACKLAST bit must also be controlled.
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