T32UC3L0128_14 Datasheet, PDF (191/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

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Figure 13-2. DFLLIF Block Diagram
COARSE
8
FINE
9
DFLL
CLK_DFLL
CSTEP
FSTEP
8+9
IMUL
FMUL
32
FREQUENCY
TUNER
DFLLLOCKF
DFLLLOCKLOSTF
DFLLLOCKC
DFLLLOCKA
DFLLLOCKLOSTC
DFLLLOCKLOSTA
CLK_DFLLIF_DITHER
CLK_DFLLIF_REF
13.5.4.1
13.5.4.2
13.5.4.3
13.5.4.4
Enabling the DFLL
The DFLL is enabled by writing a one to the Enable bit (EN) in the DFLLn Configuration Register
(DFLLnCONF). No other bits or fields in DFLLnCONF must be changed simultaneously, or
before the DFLL is enabled.
Internal synchronization
Due to multiple clock domains in the DFLLIF, values in the DFLLIF configuration registers need
to be synchronized to other clock domains. The status of this synchronization can be read from
the Power and Clocks Status Register (PCLKSR). Before writing to a DFLLIF configuration reg-
ister, the user must check that the DFLLn Synchronization Ready bit (DFLLnRDY) in PCLKSR is
set. When this bit is set, the DFLL can be configured, and CLK_DFLL is ready to be used. Any
write to a DFLLIF configuration register while DFLLnRDY is cleared will be ignored.
Before reading the value in any of the DFLL configuration registers a one must be written to the
Synchronization bit (SYNC) in the DFLLn Synchronization Register (DFLLnSYNC). The DFLL
configuration registers are ready to be read when PCLKSR.DFLLnRDY is set.
Disabling the DFLL
The DFLL is disabled by writing a zero to DFLLnCONF.EN. No other bits or fields in DFLLn-
CONF must be changed simultaneously.
After disabling the DFLL, PCLKSR.DFLLnRDY will not be set. It is not required to wait for
PCLKSR.DFLLnRDY to be set before re-enabling the DFLL.
Open loop operation
After enabling the DFLL, open loop mode is selected by writing a zero to the Mode Selection bit
(MODE) in DFLLnCONF. When operating in open loop mode the output frequency of the DFLL
will be determined by the values written to the Coarse Calibration Value field (COARSE) and the
Fine Calibration Value field (FINE) in the DFLLnCONF register. When writing to COARSE and
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