T32UC3L0128_14 Datasheet, PDF (203/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

AT32UC3L0128/256
Figure 13-7. High Resolution Prescaler Generation
Divider
Mask
HRPCLK
CKSEL
HRCOUNT
HRPEN
The HRP is enabled by writing a one to the High Resolution Prescaler Enable (HRPEN) bit in the
High Resolution Prescaler Control Register (HRPCR).
The user can select a clock source for the HRP by writing to the Clock Selection (CKSEL) field of
the HRPCR register.
The user must configure the High Resolution Prescaler Clock (HRPCLK) frequency by writing to
the High Resolution Count (HRCOUNT) field of the High Resolution Counter (HRPCR) register.
This results in the output frequency:
f_HRPCLK = f_SRC / (2*(HRCOUNT+1))
The CKSEL field can not be changed dynamically but the HRCOUNT field can be changed on-
the-fly.
13.5.14.2
Fractional prescaler
The FP generates a clock whose average frequency is more precise than the HRP. However,
this clock frequency is subject to jitter around the target clock frequency. This jitter influence can
be decreased by dividing this clock with the GCLK divider. Moreover the duty cycle of this clock
is not precisely 50%.
Figure 13-8. Fractional Prescaler Generation
Divider
Mask
FPCLK
CKSEL
FPMUL FPDIV
FPEN
The FP is enabled by writing a one to the FPEN bit in the Fractional Prescaler Control Register
(FPCR).
The user can select a clock source for the FP by writing to the CKSEL field of the FPCR register.
32145C–06/2013
203