T32UC3L0128_14 Datasheet, PDF (152/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

12.3 Block Diagram
Figure 12-1. PM Block Diagram
Main Clock Sources
Interrupts
AT32UC3L0128/256
Synchronous
Clock Generator
Synchronous
clocks
CPU, HSB,
PBx
Sleep Controller
Sleep
Instruction
Reset Sources
Power-on Reset
Detector(s)
External Reset Pin
Reset Controller
Resets
12.4 I/O Lines Description
Table 12-1.
Name
RESET_N
I/O Lines Description
Description
Reset
Type
Input
Active Level
Low
12.5 Product Dependencies
12.5.1 Interrupt
The PM interrupt line is connected to one of the interrupt controllers internal sources. Using the
PM interrupt requires the interrupt controller to be configured first.
12.5.2
Clock Implementation
In AT32UC3L0128/256, the HSB shares source clock with the CPU. Write attempts to the HSB
Clock Select register (HSBSEL) will be ignored, and it will always read the same as the CPU
Clock Select register (CPUSEL).
The PM bus interface clock (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled it can only be re-
enabled by a reset.
12.5.3
Power Considerations
The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O lines“
power configuration.
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