T32UC3L0128_14 Datasheet, PDF (642/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

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27.5.4 Interrupts
The ACIFB interrupt request line is connected to the interrupt controller. Using the ACIFB inter-
rupt requires the interrupt controller to be programmed first.
27.5.5
Peripheral Events
The ACIFB peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details.
27.5.6
Debug Operation
When an external debugger forces the CPU into debug mode, the ACIFB continues normal
operation. If the ACIFB is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during debugging.
27.6
Functional Description
The ACIFB is enabled by writing a one to the Control Register Enable bit (CTRL.EN). Addition-
ally, the comparators must be individually enabled by programming the MODE field in the AC
Configuration Register (CONFn.MODE).
The results from the individual comparators can either be used directly (normal mode), or the
results from two comparators can be grouped to generate a comparison window (window mode).
All comparators need not be in the same mode, some comparators may be in normal mode,
while others are in window mode. There are restrictions on which AC channels that can be
grouped together in a window pair, see Section 27.6.5.
27.6.1
Analog Comparator Operation
Each AC channel can be in one of four different modes, determined by CONFn.MODE:
• Off
• Continuous Measurement Mode (CM)
• User Triggered Single Measurement Mode (UT)
• Event Triggered Single Measurement Mode (ET)
After being enabled, a startup time defined in CTRL.SUT is required before the result of the
comparison is ready. The GCLK is used for measuring the startup time of a comparator,
During the startup time the AC output is not available. When the ACn Ready bit in the Status
Register (SR.ACRDYn) is one, the output of ACn is ready. In window mode the result is avail-
able when both the comparator outputs are ready (SR.ACRDYn=1 and SR.ACRDYn+1=1).
27.6.1.1
Continuous Measurement Mode
In CM, the Analog Comparator is continuously enabled and performing comparisons. This
ensures that the result of the latest comparison is always available in the ACn Current Compari-
son Status bit in the Status Register (SR.ACCSn). Comparisons are done on every positive
edge of GCLK.
CM is enabled by writing CONFn.MODE to 1. After the startup time has passed, a comparison is
done and SR is updated. Appropriate peripheral events and interrupts are also generated. New
comparisons are performed continuously until the CONFn.MODE field is written to 0.
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