T32UC3L0128_14 Datasheet, PDF (722/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

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30.6.6 Interrupts
To make the CPU able to do other things while waiting for the aWire UART user interface to fin-
ish its operations the aWire UART user interface supports generating interrupts. All status bits in
the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED
bits.
To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable
Register (IER). Upon the next zero to one transition of this SR bit the aWire UART user interface
will flag this interrupt to the CPU. To clear the interrupt the user must write a one to the corre-
sponding bit in the Status Clear Register (SCR).
Interrupts can be disabled by writing a one to the corresponding bit in the Interrupt Disable Reg-
ister (IDR). The interrupt Mask Register (IMR) can be read to check if an interrupt is enabled or
disabled.
30.6.7
Using the Peripheral DMA Controller
To relieve the CPU of data transfers the aWire UART user interface support using the Peripheral
DMA controller.
To transmit using the Peripheral DMA Controller do the following:
1. Setup the aWire UART user interface in transmit mode.
2. Setup the Peripheral DMA Controller with buffer address and length, use byte as trans-
fer size.
3. Enable the Peripheral DMA Controller.
4. Wait until the Peripheral DMA Controller is done.
To receive using the Peripheral DMA Controller do the following:
1. Setup the aWire UART user interface in receive mode
2. Setup the Peripheral DMA Controller with buffer address and length, use byte as trans-
fer size.
3. Enable the Peripheral DMA Controller.
4. Wait until the Peripheral DMA Controller is ready.
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