T32UC3L0128_14 Datasheet, PDF (27/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

AT32UC3L0128/256
Table 4-3.
Reg #
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112-191
192-255
System Registers (Continued)
Address
Name
Function
360
MPUPSR2
MPU Privilege Select Register region 2
364
MPUPSR3
MPU Privilege Select Register region 3
368
MPUPSR4
MPU Privilege Select Register region 4
372
MPUPSR5
MPU Privilege Select Register region 5
376
MPUPSR6
MPU Privilege Select Register region 6
380
MPUPSR7
MPU Privilege Select Register region 7
384
MPUCRA
Unused in this version of AVR32UC
388
MPUCRB
Unused in this version of AVR32UC
392
MPUBRA
Unused in this version of AVR32UC
396
MPUBRB
Unused in this version of AVR32UC
400
MPUAPRA
MPU Access Permission Register A
404
MPUAPRB
MPU Access Permission Register B
408
MPUCR
MPU Control Register
412
SS_STATUS Secure State Status Register
416
SS_ADRF
Secure State Address Flash Register
420
SS_ADRR
Secure State Address RAM Register
424
SS_ADR0
Secure State Address 0 Register
428
SS_ADR1
Secure State Address 1 Register
432
SS_SP_SYS Secure State Stack Pointer System Register
436
SS_SP_APP Secure State Stack Pointer Application Register
440
SS_RAR
Secure State Return Address Register
444
SS_RSR
Secure State Return Status Register
448-764
Reserved
Reserved for future use
768-1020
IMPL
IMPLEMENTATION DEFINED
4.5 Exceptions and Interrupts
In the AVR32 architecture, events are used as a common term for exceptions and interrupts.
AVR32UC incorporates a powerful event handling scheme. The different event sources, like Ille-
gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined
behavior when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execution is passed
to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are
placed sequentially in the code space starting at the address specified by EVBA, with four bytes
between each handler. This gives ample space for a jump instruction to be placed there, jump-
ing to the event routine itself. A few critical handlers have larger spacing between them, allowing
the entire event routine to be placed directly at the address specified by the EVBA-relative offset
generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR)
addresses. This allows the interrupt controller to directly specify the ISR address as an address
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