T32UC3L0128_14 Datasheet, PDF (608/852 Pages) ATMEL Corporation – Compact Single-cycle RISC Instruction Set Including DSP Instructions

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To start converting data the user can either manually start a conversion sequence by writing a
one to the START bit in the Control Register (CR.START) or configure an automatic trigger to
initiate the conversions. The automatic trigger can be configured to trig on many different condi-
tions. Refer to Section 26.8.1 for details.
The result of the conversion is stored in the Last Converted Data Register (LCDR) as they
become available, overwriting the result from the previous conversion. To avoid data loss if more
than one channel is enabled, the user must read the conversion results as they become avail-
able either by using an interrupt handler or by using a Peripheral DMA channel to copy the
results to memory. Failing to do so will result in an Overrun Error condition, indicated by the
OVRE bit in the Status Register (SR).
To use an interrupt handler the user must enable the Data Ready (DRDY) interrupt request by
writing a one to the corresponding bit in the Interrupt Enable Register (IER). To clear the inter-
rupt after the conversion result is read, the user must write a one to the corresponding bit in the
Interrupt Clear Register (ICR). See Section 26.6.11 for details.
To use a Peripheral DMA Controller channel the user must configure the Peripheral DMA Con-
troller appropriately. The Peripheral DMA Controller will, when configured, automatically read
converted data as they become available. There is no need to manually clear any bits in the
Interrupt Status Register as this is performed by the hardware. If an Overrun Error condition hap-
pens during DMA operation, the OVRE bit in the SR will be set.
26.6.3
ADC Resolution
The Analog-to-Digital Converter cell supports 8-bit or 10-bit resolution, which can be extended to
11-bit and 12-bit with the Enhanced Resolution Mode. The resolution is selected by writing the
selected resolution value to the RES field in the ADC Configuration Register (ACR). See Section
26.9.3.
By writing a zero to the RES field, the ADC switches to the lowest resolution and the conversion
results can be read in the eight lowest significant bits of the Last Converted Data Register
(LCDR). The four highest bits of the Last Converted Data (LDATA) field in the LCDR register
reads as zero. Writing a one to the RES field enables 10-bit resolution, the optimal resolution for
both sampling speed and accuracy. Writing two or three automatically enables Enhanced Reso-
lution Mode with 11-bit or 12-bit resolution, see Section 26.6.4 for details.
When a Peripheral DMA Controller channel is connected to the ADCIFB in 10-bit, 11-bit, or 12-
bit resolution mode, a transfer size of 16 bits must be used. By writing a zero to the RES field,
the destination buffers can be optimized for 8-bit transfers.
26.6.4
Enhanced Resolution Mode
The Enhanced Resolution Mode is automatically enabled when 11-bit or 12-bit mode is selected
in the ADC Configuration Register (ACR). In this mode the ADCIFB will trade conversion perfor-
mance for accuracy by averaging multiple samples.
To be able to increase the accuracy by averaging multiple samples it is important that some
noise is present in the input signal. The noise level should be between one and two LSB peak-
to-peak to get good averaging performance.
The performance cost of enabling 11-bit mode is 4 ADC samples, which reduces the effective
ADC performance by a factor 4. For 12-bit mode this factor is 16. For 12-bit mode the effective
sample rate is maximum ADC sample rate divided by 16.
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