AT17LV65_14 Datasheet, PDF (7/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

3. Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA
device control signals. All FPGA devices can control the entire configuration process and retrieve data from the
configuration EEPROM without requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV configurator. If CE is held
High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High
again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document
will describe RESET/OE.
4. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
5. Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory.
 The DATA output of the AT17LV configurator drives DIN of the FPGA devices.
 The master FPGA CCLK output drives the CLK input of the AT17LV configurator.
 The CEO output of any AT17LV configurator drives the CE input of the next configurator in a cascaded
chain of EEPROMs.
 SER_EN must be connected to V_CC (except during ISP).
 The READY⁽¹⁾ pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
Note: 1. This pin is not available for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
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Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014