English
Language : 

AT17LV65_14 Datasheet, PDF (11/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory
◁
Table 10-5. AC Characteristics when Cascading for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
Symbol
TCDF(2)
TOCK(1)
TOCE(1)
TOOE(1)
FMAX
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
Min
Max
60
60
60
45
8
AT17LV512/010/002/040
Min
Max
Units
50
ns
55
ns
40
ns
35
ns
10
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Table 10-6. AC Characteristics for VCC = 5V ± 10%
Symbol
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
THCE
THOE
FMAX
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(To Guarantee Proper Counting)
CE Hold Time from CLK
(To Guarantee Proper Counting)
OE High Time
(Guarantees Counter is Reset)
Maximum Clock Frequency
AT17LV65/128/256(3)
Min
Max
35
45
55
0
50
20
20
40
0
20
12.5
AT17LV512/010/002/040
Min
Max
Units
35
ns
45
ns
50
ns
0
ns
50
ns
20
ns
20
ns
25
ns
0
ns
20
ns
15
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET] 11
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
 ▷