AT17LV65_14 Datasheet, PDF (4/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Table 1-2. Pin Configurations
Name
AT17LV65/128/256⁽²⁾ AT17LV512/010
8-lead
8-lead
DIP/LAP/ 20-lead 20-lead DIP/ 20-lead
I/O SOIC PLCC SOIC LAP PLCC
8-lead
LAP
AT17LV002
AT17LV040
20-lead 20-lead 44-lead
PLCC SOIC TQFP
44-lead
TQFP
DATA
I/O
1
2
2
1
2
1
2
1
40
40
CLK
I
2
4
4
2
4
2
4
3
43
43
WP1
I
–
–
–
–
5
–
5
–
7
–
RESET/OE I
3
6
6
3
6
3
6
8
13
13
WP2
I
–
–
–
–
7
–
7
–
–
–
CE
I
4
8
8
4
8
4
8
10
15
15
GND
5
10
10
5
10
5
10
11
18
18
CEO⁽¹⁾
O
13
6
14
14
6
14
6
14
21
21
A2
I
–
READY
O
–
–
–
–
15
–
15
–
23
23
SER_EN
I
7
17
17
7
17
7
17
18
35
35
V_CC
8
20
20
8
20
8
20
20
38
38
Notes: 1. The CEO feature is not available on the AT17LV65 (NRND).
2. The AT17LV65 and AT17LV128 are not recommended for new designs.
4
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014