AT17LV65_14 Datasheet, PDF (17/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

12.2 8P3 – PDIP
1
N
Top View
E
E1
.381
Gage Plane
c
eA
End View
D
e
D1
A2 A
A1
b3
4 PLCS
b2
L
b _v 0.254 m C
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
A2
b
b2
b3
c
D
D1
E
E1
e
eA
L
MIN NOM MAX NOTE
-
-
5.334 2
0.381 -
-
2.921 3.302 4.953
0.356 0.457 0.559 5
1.143 1.524 1.778 6
0.762 0.991 1.143 6
0.203 0.254 0.356
9.017 9.271 10.160 3
0.127 0.000 0.000 3
7.620 7.874 8.255 4
6.096 6.350 7.112 3
2.540 BSC
7.620 BSC
4
2.921 3.302 3.810 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
Package Drawing Contact:
[e-mail]
TITLE
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
07/31/14
GPC DRAWING NO. REV.
PTC
8P3
E
AT17LV65/128/256/512/010/002/040 [DATASHEET] 17
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014