AT17LV65_14 Datasheet, PDF (18/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

12.3 8S1 – SOIC
C
1
E
E1
N
L
TOP VIEW
e
b
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
Ø
END VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN
A
1.35
A1 0.10
NOM
–
–
MAX
1.75
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1 3.81
–
3.99
E
5.79
–
6.20
e
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
NOTE
Package Drawing Contact:
[e-mail]
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
6/22/11
DRAWING NO. REV.
SWB
8S1
G
18 AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014