AT17LV65_14 Datasheet, PDF (12/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

Table 10-7. AC Characteristics When Cascading for V_CC = 5V ± 10%
AT17LV65/128/256⁽³⁾
Symbol
T_CDF(2)
T_OCK(1)
T_OCE(1)
T_OOE(1)
F_MAX
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
Min
Max
50
40
35
35
10
AT17LV512/010/002/040
Min
Max
50
40
35
30
12.5
Units
ns
ns
ns
ns
MHz
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Figure 10-1. AC Waveforms
CE
TSCE
RESET/OE
CLK
DATA
TOE
TCE
TLC
THC
TCAC
TOH
TSCE
THCE
THOE
TDF
TOH
Figure 10-2. AC Waveforms when Cascading
RESET/OE
CE
CLK
DATA
CEO
TCDF
LAST BIT
TOCK
TOCE
12 AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
TOCE
TOOE
FIRST BIT