 English |
|
|
|
|
|
|
|
| AT17LV65_14 Datasheet, PDF (6/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory | |||
| |||
| ◁ |
2. Block Diagram
Figure 2-1. Block Diagram
SER_EN
WP1(2)
WP2(2)
Programming
Mode Logic
Programming
Data Shift
Register
Power On
Reset
Row Decoder
EEPROM
Cell Matrix
Column Decoder
TC
CLK READY(2) REST/OE (WP(1))
CE
CEO(3) (A2)
DATA
Notes: 1. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
2. This pin is only available on AT17LV512, AT17LV010, and AT17LV002.
3. The CEO feature is not available on the AT17LV65 (NRND).
6
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese