AT17LV65_14 Datasheet, PDF (20/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

12.5 20S2 – SOIC
C
10
1
E1 E
E1
11
A1
TOP VIEW
e
20
b
A2
A
L
END VIEW
D
Notes:
SIDE VIEW
1. This drawing is for general information only. Refer to JEDEC Drawing
MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold flash, protrusions or gate burrs. Mold
flash, protrustions or gate burrs shall not exceed 0.15 mm per end.
Diminsion E1 does not include interlead flash or protursion. Interlead flash
or protrusion shall not exceed 0.25 mm per side.
3. The package top may be smaller than the package bottom. Dimensions D
and E1 are determinded at the outermost extremes of the plastic body
exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. The dimensions apply to the flat section of the lead between 0.10 to
0.25 mm from the lead tip.
5. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar
protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum
material condition. The dambar may not be located on the lower radius of
the foot.
6. ‘A1’ is defined as the vertical distance from the seating plane to the lowest
point on the package body excluding the lid or thermal enhancement on the
cavity down package configuration.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
12.80 BSC
2,3
E1
7.50 BSC
2,3
E
10.30 BSC
A
-
- 2.65
A1
0.10 - 0.30 6
A2
2.05 -
-
e
1.27 BSC
b
0.31 - 0.51 4,5
L
0.40 - 1.27
C
0.20
- 0.33
4
Package Drawing Contact:
[e-mail]
TITLE
20S2, 20-lead, 0.300” Wide Body, Plastic
Gull Wing Small Outline Package (SOIC)
GPC
SRJ
DRAWING NO.
20S2
7/1/14
REV.
E
20 AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014