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AT17LV65_14 Datasheet, PDF (5/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory
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Figure 1-1. Pinouts(1)
8-lead LAP
(Top View)
8-lead JEDEC SOIC
(Top View)
8-lead PDIP
(Top View)
DATA 1
CLK 2
(WP(2)) RESET/OE 3
CE 4
8 VCC
DATA 1
7 SER_EN
CLK 2
6 CEO (A2) (WP(2)) RESET/OE
3
5 GND
CE 4
8
VCC
DATA 1
7 SER_EN
6 CEO (A2)
CLK 2
5
GND
(WP(2)) RESET/OE 3
CE 4
8
VCC
7 SER_EN
6 CEO (A2)
5 GND
20-lead PLCC
(Top View)
44-lead TQFP
(Top View)
AT17LV002 Only
CLK 4
(WP1(3)) NC 5
(WP1(2)) RESET/OE 6
(WP2(3)) NC 7
CE 8
18 NC
17 SER_EN
16 NC
15 NC (READY(3))
14 CEO(4) (A2)
NC
1
NC
2
NC
3
NC
4
NC
5
NC
6
(WP1(1)) NC
7
NC
8
NC
9
NC
10
NC
11
33
NC
32
NC
31
NC
30
NC
29
NC
28
NC
27
NC
26
NC
25
NC
24
NC
23
READY
20-lead SOIC
(Top View)
AT17LV65/128/256 Only(5)
NC
1
DATA
2
NC
3
CLK
4
NC
5
RESET/OE
6
NC
7
CE
8
NC
9
GND
10
20
VCC
19
NC
18
NC
17
SER_EN
16
NC
15
NC
14
CEO (A2)
13
NC
12
NC
11
NC
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
20-lead SOIC
(Top View)
AT17LV002 Only
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
NC
SER_EN
NC
NC
NC
NC
CEO(4)
NC
GND
Notes:
1. Drawings are not to scale.
2. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
3. This pin is only available on the AT17LV512/010/002.
4. This pin is not available on the AT17LV65 (NRND).
5. The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
5
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
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