AT17LV65_14 Datasheet, PDF (3/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

1. Pin Configuration and Descriptions
Table 1-1. Pin Descriptions
Pin
DATA
CLK
WP1
RESET/OE
WP
WP2
CE
Description
Three-state Data Output for Configuration. Open-collector bi-directional pin for
programming.
Clock Input. Used to increment the internal address and bit counter for reading and
programming.
Write Protect (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
Write Protect Input (when CE is Low) during programming only (SER_EN Low). When WP is
Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on the AT17LV65 (NRND),
AT17LV128 (NRND), and the AT17LV256.
Write Protect (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on the AT17LV512/010.
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
Low).
GND
CEO
A2
READY
SER_EN
V_CC
Ground. A 0.2μF decoupling capacitor between V_CC and GND is recommended.
Chip Enable Output (Active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV devices, the CEO pin of one device
must be connected to the CE input of the next device in the chain. It will stay Low as long as
CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again. This CEO feature is not available on the
AT17LV65 (NRND).
Device Selection Input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
Open Collector Reset State Indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7k pull-up resistor when this pin is used.
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V_CC.
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
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Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014