AT17LV65_14 Datasheet, PDF (19/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

12.4 20J – PLCC
1.14(0.045) X 45°
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
e
E1 E
B
D1
D
D2/E2
B1
A2
A1
A
0.51(0.020)MAX
45° MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A
4.191
–
4.572
A1 2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1 8.890
–
9.042 Note 2
E
9.779
–
10.033
E1 8.890
–
9.042 Note 2
D2/E2 7.366
–
8.382
B
0.660
–
0.813
B1 0.330
–
0.533
e
1.270 TYP
Package Drawing Contact:
[e-mail]
10/04/01
TITLE
DRAWING NO. REV.
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
B
AT17LV65/128/256/512/010/002/040 [DATASHEET] 19
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014