AT17LV65_14 Datasheet, PDF (16/23 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

12. Packaging Information
12.1 8CN4 – LAP
Marked Pin1 Indentifier
E
D
Top View
A
A1
Side View
0.10 mm
TYP
8
e
7
L1
1
2
6
3
5
4
e1
L
Bottom View
Pin1 Corner
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A
0.94
1.04 1.14
A1
0.30
0.34
0.38
b
b
0.45
0.50 0.55
1
D
5.89
5.99
6.09
E
5.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
L
0.95
1.00 1.05
1
L1
1.25
1.30 1.35
1
Note:
1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
Package Drawing Contact:
[e-mail]
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
GPC
2/15/08
DRAWING NO. REV.
DMH
8CN4
D
16 AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014