EP20K400EFI672-2X Datasheet, PDF (96/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 76. EP20K200E Minimum Pulse Width Timing Parameters
Symbol
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
-1
Min
Max
1.36
1.36
0.18
0.18
1.36
1.36
1.18
0.95
-2
Min
Max
2.44
2.44
0.19
0.19
2.44
2.44
1.48
1.17
Table 77. EP20K200E External Timing Parameters
Symbol
t_{I N S U}
t_{I N H}
t_{O U T C O}
t_{I N S U P L L}
t_{I N H P L L}
t_{O U T C O P L L}
-1
Min
Max
2.24
0.00
2.00
5.12
2.13
0.00
0.50
3.01
-2
Min
Max
2.35
0.00
2.00
5.62
2.07
0.00
0.50
3.36
-3
Unit
Min
Max
2.65
ns
2.65
ns
0.21
ns
0.21
ns
2.65
ns
2.65
ns
1.76
ns
1.41
ns
-3
Unit
Min
Max
2.47
ns
0.00
ns
2.00
6.11
ns
-
ns
-
ns
-
-
ns
96
Altera Corporation