EP20K400EFI672-2X Datasheet, PDF (70/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figures 38 and 39 show the asynchronous and synchronous timing
waveforms, respectively, for the ESB macroparameters in Table 31.
Figure 38. ESB Asynchronous Timing Waveforms
ESB Asynchronous Read
RE
Rdaddress
Data-Out
a0
d0
a1
d1
a2
t_ESBARC
d2
ESB Asynchronous Write
WE
Data-In
Wraddress
a0
din0
t_ESBWASU
Data-Out
t_ESBWP
t_ESBWDSU
t_ESBWCCOMB
a1
din0
din1
t_ESBWDH
t_ESBWAH
t_ESBDD
din1
a3
d3
a2
dout2
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Altera Corporation