EP20K400EFI672-2X Datasheet, PDF (64/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 29. APEX 20KE Device DC Operating Conditions Notes (7), (8), (9)
Symbol
Parameter
Conditions
Min
V _IH
V _IL
V _OH
V _OL
I_I
I _OZ
I _CC0
R _CONF
High-level LVTTL, CMOS, or 3.3-V
PCI input voltage
Low-level LVTTL, CMOS, or 3.3-V
PCI input voltage
3.3-V high-level LVTTL output
voltage
I_OH = –12 mA DC,
V_CCIO = 3.00 V (11)
3.3-V high-level LVCMOS output I_OH = –0.1 mA DC,
voltage
V_CCIO = 3.00 V (11)
3.3-V high-level PCI output voltage I_OH = –0.5 mA DC,
V_CCIO = 3.00 to 3.60 V
(11)
2.5-V high-level output voltage
3.3-V low-level LVTTL output
voltage
3.3-V low-level LVCMOS output
voltage
3.3-V low-level PCI output voltage
I_OH = –0.1 mA DC,
V_CCIO = 2.30 V (11)
I_OH = –1 mA DC,
V_CCIO = 2.30 V (11)
I_OH = –2 mA DC,
V_CCIO = 2.30 V (11)
I_OL = 12 mA DC,
V_CCIO = 3.00 V (12)
I_OL = 0.1 mA DC,
V_CCIO = 3.00 V (12)
I_OL = 1.5 mA DC,
V_CCIO = 3.00 to 3.60 V
(12)
2.5-V low-level output voltage
Input pin leakage current
Tri-stated I/O pin leakage current
V_CC supply current (standby)
(All ESBs in power-down mode)
I_OL = 0.1 mA DC,
V_CCIO = 2.30 V (12)
I_OL = 1 mA DC,
V_CCIO = 2.30 V (12)
I_OL = 2 mA DC,
V_CCIO = 2.30 V (12)
V_I = 4.1 to –0.5 V (13)
V_O = 4.1 to –0.5 V (13)
V_I = ground, no load, no
toggling inputs, -1 speed
grade
V_I = ground, no load, no
toggling inputs,
-2, -3 speed grades
Value of I/O pin pull-up resistor
before and during configuration
V_CCIO = 3.0 V (14)
V_CCIO = 2.375 V (14)
V_CCIO = 1.71 V (14)
1.7, 0.5 × V_CCIO
(10)
–0.5
2.4
V_CCIO – 0.2
0.9 × V_CCIO
2.1
2.0
1.7
–10
–10
20
30
60
Typ
Max
4.1
0.8, 0.3 × V_CCIO
(10)
0.4
0.2
0.1 × V_CCIO
0.2
0.4
0.7
10
10
10
5
50
80
150
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
mA
mA
kΩ
kΩ
kΩ
64
Altera Corporation