EP20K400EFI672-2X Datasheet, PDF (5/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 5. APEX 20K FineLine BGA Package Options & I/O Count Notes (1), (2)
Device
144 Pin
324 Pin
484 Pin
672 Pin
1,020 Pin
EP20K30E
93
128
EP20K60E
93
196
EP20K100
252
EP20K100E
93
246
EP20K160E
316
EP20K200
382
EP20K200E
376
376
EP20K300E
408
EP20K400
502 (3)
EP20K400E
488 (3)
EP20K600E
508 (3)
588
EP20K1000E
508 (3)
708
EP20K1500E
808
Notes to Tables 4 and 5:
(1) I/O counts include dedicated input and clock pins.
(2) APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
(3) This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device
Package Information Data Sheet for detailed package size information.
Table 6. APEX 20K QFP, BGA & PGA Package Sizes
Feature
Pitch (mm)
Area (mm²)
Length × Width
(mm × mm)
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
0.50
484
22 × 22
0.50
924
30.4 × 30.4
0.50
1,218
34.9 × 34.9
1.27
1,225
35 × 35
1.27
2,025
45 × 45
–
3,906
62.5 × 62.5
Table 7. APEX 20K FineLine BGA Package Sizes
Feature
Pitch (mm)
Area (mm²)
Length × Width (mm × mm)
144 Pin
1.00
169
13 × 13
324 Pin
1.00
361
19 × 19
484 Pin
1.00
529
23 × 23
672 Pin
1.00
729
27 × 27
1,020 Pin
1.00
1,089
33 × 33
Altera Corporation
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