EP20K400EFI672-2X Datasheet, PDF (41/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 26. APEX 20KE Bidirectional I/O Registers
Row, Column, FastRow, 4 Dedicated
or Local Interconnect Clock Inputs
4 Dedicated Peripheral Control
Inputs
Bus
Notes (1), (2)
OE Register
DQ
VCC
ENA
CLRN
OE[7..0]
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
12
4 _VCC
CLK[1..0]
CLK[3..0]
ENA[5..0]
CLRn[1..0]
Input Pin to
Core Delay (1)
Input Pin to
Core Delay (1)
Core to Output
Register Delay
Input Pin to Input
Register Delay
Output Register
DQ
ENA
CLRN/
PRN
VCC
Clock Enable
Delay (1)
VCC
Output Register
tCO Delay
Open-Drain
Output
Slew-Rate
Control
VCC
Chip-Wide
Reset _{Input Register}
DQ
VCC
ENA
CLRN
Input Pin to
Core Delay (1)
VCCIO
Optional
PCI Clamp
Chip-Wide
Reset
Notes to Figure 26:
(1) This programmable delay has four settings: off and three levels of delay.
(2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Altera Corporation
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