EP20K400EFI672-2X Datasheet, PDF (51/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
t_SKEW
t_JITTER
t_INCLKSTB
Skew delay between related
ClockLock/ClockBoost-generated clocks
Jitter on ClockLock/ClockBoost-generated clock
(5)
Input clock stability (measured between adjacent
clocks)
500
ps
200
ps
50
ps
Notes to Table 15:
(1) The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
(2) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4) The jitter specification is measured under long-term observation.
(5) If the input clock stability is 100 ps, t_JITTER is 250 ps.
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
Symbol
f_OUT
f _CLK1
f _CLK2
f _CLK4
t _OUTDUTY
f _CLKDEV
t_R
t_F
t _LOCK
t _SKEW
t _JITTER
t _INCLKSTB
Parameter
Output frequency
Input clock frequency (ClockBoost clock multiplication
factor equals 1)
Input clock frequency (ClockBoost clock multiplication
factor equals 2)
Input clock frequency (ClockBoost clock multiplication
factor equals 4)
Duty cycle for ClockLock/ClockBoost-generated clock
Input deviation from user specification in the Quartus II
software (ClockBoost clock multiplication factor equals
one) (1)
Input rise time
Input fall time
Time required for ClockLock/ ClockBoost to acquire
lock (3)
Skew delay between related ClockLock/ ClockBoost-
generated clock
Jitter on ClockLock/ ClockBoost-generated clock (4)
Input clock stability (measured between adjacent
clocks)
Min
25
25
16
10
40
500
Max
170
170
80
34
60
25,000 (2)
5
5
10
500
200
50
Unit
MHz
MHz
MHz
MHz
%
PPM
ns
ns
µs
ps
ps
ps
Altera Corporation
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