EP20K400EFI672-2X Datasheet, PDF (38/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 10 describes the APEX 20K programmable delays and their logic
options in the Quartus II software.
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
Input pin to core delay
Input pin to input register delay
Core to output register delay
Output register t_CO delay
Quartus II Logic Option
Decrease input delay to internal cells
Decrease input delay to input register
Decrease input delay to output register
Increase delay to output pin
The Quartus II software compiler can program these delays automatically
to minimize setup time while providing a zero hold time. Figure 25 shows
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
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Altera Corporation