EP20K400EFI672-2X Datasheet, PDF (73/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 31. APEX 20K f_MAX Timing Parameters (Part 2 of 2)
Symbol
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
t_F1-4
t_F5-20
t_F20+
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
Parameter
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB macrocell input to non-registered output
ESB macrocell register setup time before clock
ESB macrocell register clock-to-output delay
Fanout delay using local interconnect
Fanout delay using MegaLab Interconnect
Fanout delay using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
LE preset pulse width
Clock high time
Clock low time
Write pulse width
Read pulse width
Tables 32 and 33 describe APEX 20K external timing parameters.
Table 32. APEX 20K External Timing Parameters Note (1)
Symbol
t_INSU
t_INH
t_OUTCO
Clock Parameter
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Table 33. APEX 20K External Bidirectional Timing Parameters Note (1)
Symbol
t_INSUBIDIR
t_INHBIDIR
t_OUTCOBIDIR
t_XZBIDIR
t_ZXBIDIR
Parameter
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
Clock-to-output delay for bidirectional pins with global clock at IOE
register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
Conditions
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
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