EP20K400EFI672-2X Datasheet, PDF (71/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 39. ESB Synchronous Timing Waveforms
ESB Synchronous Read
WE
Rdaddress
CLK
a0
t_ESBDATASU
Data-Out
a1
t_ESBDATAH
t_ESBDATACO2
a2
t_ESBARC
d1
a3
d2
ESB Synchronous Write (ESB Output Registers Used)
WE
Data-In
din1
din2
din3
Wraddress a0
CLK
Data-Out
a1
t_ESBWESU
a2
t_ESBDATASU
t_ESBDATAH
a3
t_ESBWEH
dout0
dout1
t_ESBSWC
din1
t_ESBDATACO1
din2
a2
din3
din2
Figure 40 shows the timing model for bidirectional I/O pin timing.
Altera Corporation
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